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| PRODUCT INFORMATION DPS 9450A Feb/2002 DPS 9450A Display Processor and Scaler The DPS is a single-chip digital display processor and scaler specially designed for TV sets with matrix displays. The DPS 9450A is a new family member of the Micronas MEGAVISION(R) IC set implemented in deep submicron CMOS technology. Display Modes x Digital mode: video from the digital input x Analog mode: video/graphic/teletext from the analog RGB/YCrCb input x Softmix mode: soft mixing of the video and component input x Additional OSD can be mixed Display Format Processing x Prescaling of the input signal: horizontal scaling factor: 1.0 ... 1/64 x Upscaling of the output signal: horizontal scaling factor: 1 ... 4 (5-zone panorama generator) x Vertical scaling factor: 0.5 ... 4 x Deinterlacing with line-doubling/upscaling Video Inputs x Digital input for 50/60 I or 50/60 P signals in ITU-656 (8 bit) or ITU-601 (16 bit) x 3x8 bit YCrCb/RGB input x 2 analog RGB/YCrCb inputs for Teletext, graphic, 480p (EIA-770.2, 1080i/720p reduced resolution): 4 built-in ADCs (8-bit) for RGB + fastblank with 40.5 MHz sampling rate x Separate HS and VS (2x) inputs Video Processing OSD x Full 4:4:4 processing x RGB-to-YCrCb conversion x Brightness, Contrast, Saturation for analog component input x Dynamic contrast improvement (DCI) x Black level expander (BLE) x digital RGB input (6 or 12 bit / pixel) x 64 entry CLUT with 12-bit colors x Picture frame and testpattern generation x Half-contrast switch (0, 25%, 50%, 100%) Sync Processing x HS and VS outputs to synchronize - the ext. analog RGB/YCrCb source in the soft mix mode (see display modes) - ext. OSD source x Luma & chroma transition improvement x Dynamic peaking x Brightness, Contrast, Saturation, Tint x Programmable YCrCb-to-RGB matrix x Programmable characteristic on R,G,B, for -correction, Blue-stretch, White-drive x Dithering for 8- to 6-bit digital outputs Display Resolutions x 640x480 (VGA; 4:3 panel) x 852x480 (W-VGA; 16:9 panel) x 800x600 (SVGA) x 1024x768 (XGA) x 1365x768 (W-XGA) PRODUCT INFORMATION DPS 9450A Output Interface CVBS YCrCb RGB Y/C YPrPb clk HV RGB Feb/2002 x 2x18- or 24-bit RGB output: dual-pixel mode x programmable panel control signals VSP 941x DPS 9450A RGB Panel Control Miscellaneous x up to 2 PWM outputs x up to 8 general purpose I/Os x I2C interface (400 kHz) x JTAG boundary scan interface x 1.8 V and 3.3 V supply x PMQFP144 package RGB OSD, Text, Micro e. g. SDA 6000 Fig. 1: Application example: TV/VGA source XGA panel System Architecture The figure shows the block diagram of the DPS 9450A. The device has digital outputs. In principle the device comprises three major functional and clock domains parts. ITU domain Input domain XOUT CLK20/XIN RGB TDO TCK TMS TDI TEST CS SCL SDA RESET IC Interface HV HV Xtal Oscillator The functional parts are x video input processing, x scaling, and x display processing. The clock domains are x ITU domain, x input domain, and x display domain (compare the block diagram and the different shaded areas). The input and the output signals of the IC can be chosen in various configurations. 648 MHz DTO Divider CLKD: 25-81 MHz clk Test Controller CLKIN VIN/VIN2 HIN/HIN2 ITU656, ITU601, RGB/YUVIN VOUT1 HOUT1/ Clamp CLKF 24 16 ITU656 ITU601 Decoder Display domain Input Video Processing Upsampling (422 444) Line-doubling (optional) Input Sync Processing Channel Mixer Scaler and Deinterlacer lin. H/V-Scaler nonlin. H-Scaler Deinterlacing Picture Improvements LTI/CTI Peaking Blacklevel Expander Cr/RIN1 Y/GIN1 Cb/BIN1 FBL1 Cr/RIN2 Y/GIN2 Cb/BIN2 FBL2 Source Select 4 ADCs Compontent Input: Component Processing 24 RGB YC rCb Matrix Contrast Brightness Saturation Picture Settings Contrast Brightness Saturation Tint Matrix Pixel Mixer Gamma Dithering and Panel Controlling 36 RGBOUT PCK1/2 PanelCtrl 11 Digital OSD 6/12 bit Picture Frame Testpattern 12 2 RGBOSD FBOSD HCOSD Fig. 2: Block diagram of the DPS 9450A All information and data contained in this product information are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our respective order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Edition Feb. 25, 2002; Order No. 6251-591-1PI Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com www.micronas.com |
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